Altera公司的Cyclone V SoC FPGA 系列基于28nm低功耗（LP）工藝，提供需要5G收發器應用的最低功耗，和以前的產品檢驗相比，功耗降低40%.器件集成了基于ARM處理器的硬件處理器系統（HPS），具有更有效的邏輯綜合功能，收發器系列和SoC FPGA系列，從而降低系統功耗，成本和產品上市時間，主要用在工業，無線和有線通信，軍用設備和汽車市場。本文介紹了Cyclone V SoC FPGA 系列主要優勢和特性，架構圖，HPS特性以及Cyclone V SX SoC開發板主要特性，框圖和電路圖。

　　Altera’s Cyclone? V FPGAs provide the industry’s lowest system cost and power， along with performance levels that make the device family ideal for differentiating your high-volume applications. You’ll get up to 40 percent lower total power compared with the previous generation， efficient logic integration capabilities， integrated transceiver variants， and SoC FPGA variants with an ARM?-based hard processor system （HPS）。

　　The Cyclone? V devices are designed to simultaneously accommodate the shrinking power consumption， cost， and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications.

　　Enhanced with integrated transceivers and hard memory controllers， the Cyclone? V devices are suitable for applications in the industrial， wireless and wireline， military， and automotive markets.

　　Built on the 28-nm low power （LP） process technology， Altera’s Cyclone V FPGAs deliver the lowest power solution for applications requiring up to 5G transceivers. Compared to previous generations， Cyclone V FPGAs offer a 40-percent power reduction， with a balance of power reduction from all areas.

圖1.Cyclone V SoC FPGA架構圖

　　圖2.Cyclone V SoC框圖

　　硬件處理器系統（HPS）特性：

　　925 MHz， dual-core ARM? Cortex?-A9 MPCore? processor

　　Each processor core includes：

　　32 KB of L1 instruction cache， 32 KB of L1 data cache

　　Single- and double-precision floating-point unit and NEONTM media engine

　　CoreSightTM debug and trace technology

　　512 KB of shared L2 cache

　　64 KB of scratch RAM

　　Multiport SDRAM controller with support for DDR2， DDR3， and LPDDR2 and optional error correction code （ECC） support

　　8-channel direct memory access （DMA） controller

　　QSPI flash controller

　　NAND flash controller with DMA

　　SD/SDIO/MMC controller with DMA

　　2x 10/100/1000 Ethernet media access control （MAC） with DMA

　　2x USB On-The-Go （OTG） controller with DMA

　　4x I2C controller

　　2x UART

　　2x serial peripheral interface （SPI） master peripherals， 2x SPI slave peripherals

　　Up to 134 general-purpose I/O （GPIO）

　　7x general-purpose timers

　　4x watchdog timers

　　High-Bandwidth HPS-to-FPGA Interconnect Backbone

　　Although the HPS and the FPGA can operate independently， they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA? AXITM bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly， HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally， the processor can be used to configure the FPGA fabric under program control via a dedicated 32 bit configuration port.

　　HPS-to-FPGA： configurable 32， 64， or 128 bit AMBA AXI interface

　　FPGA-to-HPS： configurable 32， 64， or 128 bit AMBA AXI interface

　　FPGA-to-HPS SDRAM controller： up to 6 masters （command ports）， 4x 64 bit read data ports and 4x 64 bit write data ports

　　32 bit FPGA configuration manager

　　Cyclone V 系列產品主要優勢：

Cyclone V 系列產品主要特性:

　　Cyclone V SX SoC開發板

　　The Altera? Cyclone? V SoC Development Kit offers a quick and simple approach to develop custom ARM? processor-based SoC designs accompanied by Altera’s low-power， low-cost Cyclone V FPGA fabric.

　　Cyclone V SX SoC開發板主要特性：

　　Processor and FPGA prototyping and power measurement

　　Industrial networking protocols

　　Motor control applications*

　　Acceleration of image- and video-processing applications*

　　PCI Express? （PCIe?） x4 lane with ~1，000 MBps transfer rate （endpoint or rootport）

　　*Application-specific daughtercards， available separately， supporting a wide range of I/O and interface standards.

　　圖3. Cyclone V SX SoC開發板外形圖

　　Cyclone V SX SoC開發板包含：

　　Cyclone V SX development board

　　Featured devices

　　Cyclone V SX SoC—5CSXFC6D6F31C6N （SoC）

　　MAX? V CPLD—5M2210ZF256C4N （system controller）

　　MAX II CPLD—EPM570GF100 （embedded USB-BlasterTM II cable）

　　FPGA configuration sources

　　Embedded USB-Blaster II （JTAG） cable

　　EPCQ flash （PFL）

　　Hard processor system （HPS）

　　FPGA memory

　　1 GB DDR3 SDRAM （32 bit）

　　FPGA I/O interfaces

　　2X 10/100 Megabit Ethernet PHYs （EtherCAT）

　　PCIe Gen1 x4 female connector

　　Universal high-speed mezzanine card （HSMC）—x4 transceivers， x16 TX LVDS， x16 RX LVDS

　　One serial digital interface （SDI） channel

　　Four SMAs for one transceiver channel

　　4X push buttons

　　2X switches

　　4X LEDs

　　HPS boot sources

　　128 MB quad serial peripheral interface （SPI） flash memory

　　Removable micro-SD card flash memory

　　FPGA

　　HPS memory

　　1 GB DDR3 SDRAM （32 bit） with error correction code （ECC）

　　128 MB quad SPI flash memory

　　Micro-SD card socket with 4 GB micro-SD card flash device

　　HPS I/O interfaces

　　1X USB 2.0 On-the-Go （OTG）

　　1X 10/100/1000 Megabit Ethernet （10MbE/100MbE/1000MbE）

　　1X CAN

　　1X UART （UART to USB bridge）

　　1X real-time clock （with battery backup）

　　1X two-line text LCD

　　1-/2-channel， 20 bit delta-sigma analog-to-digital converter （Linear Technology LTC2422）

　　4X push buttons

　　4X switches

　　4X LEDs

　　Clocking

　　Four-output programmable clock generator for FPGA reference clock inputs

　　125 MHz LVDS oscillator for FPGA reference clock input

　　148.5 MHz LVDS programmable voltage-controlled crystal oscillator （VCXO） for FPGA reference clock input

　　50 MHz single-ended oscillator for FPGA and MAX V FPGA clock input

　　100 MHz single-ended oscillator for MAX V FPGA configuration clock input

　　SMA input for HPS clock

　　Power

　　Laptop DC input 14—20 V adapter

　　System monitoring circuit

　　Power （voltage， current， wattage）

　　HSMC breakout board

　　HSMC loopback board

　　Mechanical

　　Board dimensions—8.19” x 5.22”

　　Cyclone V SX FPGA Development Kit software content （downloadable from Table 2）

　　Design examples

　　Board test system （BTS）*

　　Golden System Reference Design with Board Update Portal web server

　　Complete documentation （see Table 2）

　　SoC Embedded Design Suite Standard Edition

　　ARM Development Studio 5 （DS-5?） Altera Edition Toolkit

　　Hardware-to-software handoff tools

　　Linux run-time software for application development

　　SoC hardware libraries for firmware development

　　Application examples

　　Free software supported by Quartus? Prime Lite and Standard Edition software

圖4. Cyclone V SX SoC開發板框圖

圖5. Cyclone V SX SoC開發板電路圖(1)

圖6. Cyclone V SX SoC開發板電路圖(2)

圖7. Cyclone V SX SoC開發板電路圖(3)

圖8. Cyclone V SX SoC開發板電路圖(4)

圖9. Cyclone V SX SoC開發板電路圖(5)

圖10. Cyclone V SX SoC開發板電路圖(6)

圖11. Cyclone V SX SoC開發板電路圖(7)

圖12. Cyclone V SX SoC開發板電路圖(8)

圖13. Cyclone V SX SoC開發板電路圖(9)

圖14. Cyclone V SX SoC開發板電路圖(10)

圖15. Cyclone V SX SoC開發板電路圖(11)

圖16. Cyclone V SX SoC開發板電路圖(12)

圖17. Cyclone V SX SoC開發板電路圖(13)

圖18. Cyclone V SX SoC開發板電路圖(14)

圖19. Cyclone V SX SoC開發板電路圖(15)

圖20. Cyclone V SX SoC開發板電路圖(16)

圖21. Cyclone V SX SoC開發板電路圖(17)

圖22. Cyclone V SX SoC開發板電路圖(18)

圖23. Cyclone V SX SoC開發板電路圖(19)

圖24. Cyclone V SX SoC開發板電路圖(20)

圖25. Cyclone V SX SoC開發板電路圖(21)

圖26. Cyclone V SX SoC開發板電路圖(22)

圖27. Cyclone V SX SoC開發板電路圖(23)

圖28. Cyclone V SX SoC開發板電路圖(24)

圖29. Cyclone V SX SoC開發板電路圖(25)

圖30. Cyclone V SX SoC開發板電路圖(26)

圖31. Cyclone V SX SoC開發板電路圖(27)

圖32. Cyclone V SX SoC開發板電路圖(28)

圖33. Cyclone V SX SoC開發板電路圖(29)

圖34. Cyclone V SX SoC開發板電路圖(30)

圖35. Cyclone V SX SoC開發板電路圖(31)

圖36. Cyclone V SX SoC開發板電路圖(32)

圖37. Cyclone V SX SoC開發板電路圖(33)

圖38. Cyclone V SX SoC開發板電路圖(34)

圖39. Cyclone V SX SoC開發板電路圖(35)

圖40. Cyclone V SX SoC開發板電路圖(36)

圖41. Cyclone V SX SoC開發板電路圖(37)