一個簡單的匯編程序適合于微處理器實現數字低通濾波器。
　　濾波常發生在模擬世界。不幸的是，在數字領域，工程師通常主要使用DSP（數字信號處理器），而不是8位單片機實現濾波。這個情形的發生，是因為濾波器設計的算法比大多數工程師樂于處理的算法更復雜。而且，數字濾波需要計算整形數，而不是浮點數。這引發了兩個問題。第一，有限位的舍入誤差降低了濾波器響應，甚至使它不穩定。第二，必須用整數算法處理小數值。
　　有幾種方法解決這些問題。例如，可以使用16、32和64位數的操作，或可以縮放到更好的精度。這些和其他方法通常需要更多的存儲器，造成編程經常不適于小型微處理器。文獻研究所示用C語言編寫的數字濾波固件，與用匯編語言編寫需要更多的存儲器。這個情形對存儲器資源有限的小型微處理器來講，常常是不可接受的。
　　列表1（程序見英文原文）列出了一個用8位微處理器設計單極低通數字濾波器固件的簡單方法。Freescale公司的低端MC68HC908QT2使用匯編編程器，但可以將本設計方案用于任一型號微處理器，只要其使用的也是標準匯編指令。
　　將基于廣義Z
　　變換算法的復雜設計方案放在一邊，本方案使用了一種基于遞歸方程的解決辦法。計算每個輸出信號采樣，作為輸入信號和前一個輸出信號帶相關系數的總和。遞歸方程定義一個單極低通濾波器為：Y［n］=X［n］×a0+Y［n–1］×b1，在這里X［n］和Y［n］為采樣［n］的輸入輸出值，Y［n–1］為前一采樣［n–1］的輸出值，a0和b1為減少δ控制的權重系數。系數為0《δ《1的值，a0=1–δ且b1=δ。理論上，δ為輸入信號從高電平降到低電平時，鄰近的輸出采樣之間的衰減量。可以直接指定δ值或找到濾波器所需的時間常數d，其為采樣數上升到低通濾波器穩態63.2%時的輸出。D和δ之間存在確定的關系：δ=e–1/d，在這里e為自然對數基底。前面的公式服從Y［n］=Y［n–1］+（1–δ）×（X［n］–Y［n–1］）。
　　為取代小數相乘，1–δ對匯編程序而言，用除以倒數為整數的方法更方便，F=1/（1–δ）： Y［n］=Y［n–1］+（X［n］–Y［n–1］）/F。因此，可以按照下面的步驟確定數字濾波器參數：
　　1、選擇參數F。對匯編程序而言，便于用右移實現除法運算。右移就是F值應該為2S，在此S為偏移數。讓F為8，相當于右移三位。
　　2、計算衰減：δ=1–1/F=1–1/8=0.875。
　　3、計算時間常數d=–1/lnδ=–1/ln0.875=7.49采樣。
　　公式Y［n］=Y［n–1］+（X［n］–Y［n–1］）/F決定濾波器的微處理器算法設計。算法需要三個寄存器：輸入X［n］、輸出Y［n］和一個遞增寄存器保存（X［n］–Y［n–1］）/F的值。三個寄存器的大小取決于輸入。應用中，內置的8位ADC輸出范圍從00到$FF的信號，必須經歷低通濾波器。所以輸入和輸出寄存器均為1個字節。為增加除法精度，增加一半除數到被除數。這個處理將遞增寄存器增加到2個字節。
　　用數字方法實現濾波功能提供了一致性的好處，因為器件誤差、溫度漂移和老化不會影響濾波器算法。用微處理器實現數字濾波器，增加了可調整濾波器參數的靈活性優勢，因為這個靈活性僅取決于固件。
英文原文：
　　8-bit microcontroller implements digital lowpass filter
　　A simple assembler routine fits a digital lowpass filter into a microcontroller.
　　Abel Raynus， Armatron International， Malden， MA; Edited by Charles H Small and Fran Granville -- EDN， 1/24/2008
　　Filtering occurs frequently in the analog world. Unfortunately， in the digital world， engineers apply it mainly to the DSPs （digital-signal processors） and not to the small 8-bit microcontrollers that designers commonly use. This situation occurs because the math for the filter design is more complicated than most engineers are willing to deal with. Moreover， digital filtering requires calculations on integers instead of on floating-point numbers. This scenario causes two problems. First， the rounding-off error from the limited number of bits can degrade the filter response or even make it unstable. Second， you must handle the fractional values with integer math.
　　Several ways exist to solve these issues. For example， you can use operations with 16-， 32-， and 64-bit numbers， or you can scale for better accuracy. These and other methods usually require more memory， and， as a result， the program often does not fit into a small microcontroller. A literature search shows that published digital-filter firmware is written in C. Programs in C need more memory than those written in assembler. This situation often makes them unacceptable for small microcontrollers with limited memory resources.
　　Listing 1 shows a simple engineering method to design single-pole， lowpass-digital-filter firmware for 8-bit microcontrollers. The low-end Freescale MC68HC908QT2 is the target of the assembler program， but you can apply this Design Idea to any type of microcontroller because it uses only standard assembler instructions.
　　Leaving aside the sophisticated design methods based on Z transformation with its extensive math， this idea uses another approach based on a recursive equation. You calculate each output-signal sample as the sum of the input signal and the previous output signal with corresponding coefficients. A recursive equation defines a single-pole lowpass filter as： Y［n］=X［n］×a0+Y［n–1］×b1， where X［n］ and Y［n］ are input and output values of sample ［n］， Y［n–1］ is an output value of the previous sample ［n–1］， and a0 and b1 are weight coefficients that decrement δ controls. The coefficients have the value of 0《δ《1， a0=1–δ， and b1=δ。 Physically， δ is the amount of decay between adjacent output samples when the input signal drops from a high level to a low level. You can directly specify the value of δ or find it from the desired time constant of the filter， d， which is the number of samples it takes the output to rise to 63.2% of the steady-state level for a lowpass filter. A fixed relationship exists between d and δ： δ=e–1/d， where e is the base of natural logarithms. The preceding equations yield Y［n］=Y［n–1］+（1–δ）×（X［n］–Y［n–1］）。
　　Instead of multiplying a decimal-point number， 1–δ， it is more convenient for assembler programming to divide by the reciprocal integer， F=“1/”（1–δ）： Y［n］=Y［n–1］+（
　　X［n］–Y［n–1］）/F. Thus， you can determine the digital filter’s parameters using the following steps：
　　Choose the parameter F. For assembler， it is convenient to perform division as right shifts. For right shifts， the value of F should be 2S， where S is the number of shifts. Let F equal 8， which you reach after three right shifts.
　　Calculate the decrement： δ=1–1/F=1–1/8=0.875.
　　Calculate the time constant as d=–1/lnδ=–1/ln0.875=7.49 samples.
　　The equation Y［n］=Y［n–1］+（X［n］–Y［n–1］）/F determines the design of the microcontroller’s algorithm for the filter. The algorithm needs three registers： input for X［n］， output for Y［n］， and an increment register to keep the （X［n］–Y［n–1］）/F term. The size of these registers depends on the inputs. In this application， the signals from the built-in 8-bit ADC range from 00 to $FF and must go through the lowpass filter. So， the input and the output registers are 1 byte in size. To increase the accuracy of division， add half the divisor to the dividend. This action increases the increment register to 2 bytes.
　　Numerically performing the filtering function provides the benefit of consistency because component tolerances， temperature drift， and aging do not affect the filter’s algorithm. The implementation of the digital filter in the microcontroller gives the additional benefit of flexibility to adjust the filter’s parameters， because this flexibility depends only on the firmware.
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