| Configuration | Parallel-in, Serial-out |
| Bits (#) | 8 |
| Technology Family | HC |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock Frequency (MHz) | 24 |
| IOL (Max) (mA) | 5.2 |
| IOH (Max) (mA) | -5.2 |
| ICC (Max) (uA) | 160 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of Up To –55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- 2-V to 6-V VCC Operation
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-μA Max ICC
- Typical tpd = 13 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 μA Max
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. While SH/LD\ is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
