| Resolution (Bits) | 8 |
| Number of DAC channels (#) | 1 |
| Interface type | Parallel CMOS |
| Sample/update rate (MSPS) | 100 |
| Features | Low Power |
| Rating | Catalog |
| Interpolation | 1x |
| Power consumption (Typ) (mW) | 100 |
| SFDR (dB) | 69 |
| Architecture | Current Source |
| Operating temperature range (C) | -40 to 85 |
| Reference type | Ext |
- Member of the Pin-Compatible CommsDAC? Product Family
- 100 MSPS Update Rate
- 8-Bit Resolution
- Signal-to-Noise and Distortion Ratio (SINAD) at 5 MHz: 50 dB
- Integral Nonlinearity INL: 0.25 LSB
- Differential Nonlinearity DNL: 0.25 LSB
- 1 ns Setup/Hold Time
- Glitch Energy: 5 pV-s
- Settling Time to 0.1%: 35 ns
- Differential Scalable Current Outputs: 2 mA to 20 mA
- On-Chip 1.2-V Reference
- 3-V and 5-V Single Supply Operation
- Straight Binary or Twos Complement Input
- Power Dissipation: 100 mW at 3.3 V, Sleep Mode: 17 mW at 3.3 V
- Package: 28-Pin SOIC and TSSOP
CommsDAC is a trademark of Texas Instruments.
The THS5641A is an 8-bit resolution digital-to-analog converter (DAC) optimized for video applications and digital data transmission in wired and wireless communication systems. The 8-bit DAC is a member of the CommsDAC? series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC? family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package and pinout. The THS5641A offers superior ac and dc performance while supporting update rates up to 100 MSPS.
The THS5641A operates from an analog and digital supply of 3 V to 5.5 V. Its inherent low power dissipation of 100 mW ensures that the device is well suited for portable and low power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 17 mW, thereby optimizing the power consumption for system needs.
The THS5641A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5641A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors.
The THS5641A provides a nominal full-scale differential output current of 20 mA and > 300 k
output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC.
The THS5641A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of ?40°C to 85°C.
