| Sample rate (Max) (MSPS) | 40 |
| Resolution (Bits) | 12 |
| Number of input channels | 8 |
| Interface type | Parallel LVDS |
| Analog input BW (MHz) | 300 |
| Features | Low Power |
| Rating | Catalog |
| Input range (Vp-p) | 2 |
| Power consumption (Typ) (mW) | 907 |
| Architecture | Pipeline |
| SNR (dB) | 70.5 |
| ENOB (Bits) | 11.3 |
| SFDR (dB) | 89 |
| Operating temperature range (C) | -40 to 85 |
| Input buffer | No |
- Maximum Sample Rate: 40MSPS
- 12-Bit Resolution
- No Missing Codes
- Total Power Dissipation:
Internal Reference: 888mW
External Reference: 822mW - CMOS Technology
- Simultaneous Sample-and-Hold
- 70.5dB SNR at 10MHz IF
- 3.3V Digital/Analog Supply
- Serialized LVDS Outputs
- Integrated Frame and Bit Patterns
- Option to Double LVDS Clock Output Currents
- Four Current Modes for LVDS
- Pin- and Format-Compatible Family
- TQFP-80 PowerPAD Package
The ADS5270 is a high-performance, 40MSPS, 8-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.
An integrated phase lock loop (PLL) multiplies theincoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the eight data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.
The ADS5270 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.
The device is available in a TQFP-80 PowerPAD package and is specified over a -40°C to +85°C operating range.
