| Function | Single-ended |
| Additive RMS jitter (Typ) (fs) | 300 |
| Output frequency (Max) (MHz) | 52 |
| Number of outputs | 4 |
| Output supply voltage (V) | 1.8 |
| Core supply voltage (V) | 1.8 |
| Output skew (ps) | 50 |
| Features | SINE wave |
| Operating temperature range (C) | -40 to 85 |
| Rating | Catalog |
| Output type | SINE |
| Input type | SINE |
- 1:4 Low-Jitter Clock Buffer
- Single-Ended Sine-Wave Clock Input and Outputs
- Ultralow Phase Noise and Standby Current
- Individual Clock Request Inputs for Each Output
- On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply
- Serial I2C Interface (Compatible With High-Speed Mode,
3.4 Mbit/s) - 1.8-V Device Power Supply
- Wide Temperature Range, –40°C to 85°C
- ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM
- Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm)
The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.
Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I2C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I2C.
The CDC3S04 also provides an I2C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding.
The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO.
A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see ); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of VDD_DIG.
The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order.
The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 μA). It is characterized for operation from –40°C to 85°C.
