本文主要介紹Xilinx FPGA的GTx的參考時(shí)鐘。下面就從參考時(shí)鐘的模式、參考時(shí)鐘的選擇等方面進(jìn)行介紹。

參考時(shí)鐘的模式

參考時(shí)鐘可以配置為輸入模式也可以是輸出模式，但是在運(yùn)行期間不能切換。作為輸入時(shí)，用于驅(qū)動(dòng)Quad 或者channel PLLs，作為輸出時(shí)，可以來(lái)自于同一個(gè)Quad中的任意一個(gè)channel。7系列的GTx只能作為輸入，而Ultra和Ultra+系列的還可以作為輸出。

作為輸入模式時(shí)，7系列和Ultra是通過(guò)50Ω連接到4/5MGTAVCC上，Ultra+是通過(guò)50Ω連接到MGTAVCC上。后端根據(jù)不同系列器件給到不同IBUFDS_GTE。

作為輸出模式時(shí)，可以配置為從OBUFDS_GTE3/4或者OBUFDS_GTE3/4_ADV輸出，UseOBUFDS_GTE3/4 when the RXRECCLKOUT is always derived from the same channel. UseOBUFDS_GTE3/4_ADV if the channel providing RXRECCLKOUT can change duringruntime.

參考時(shí)鐘的選擇

The GTP transceivers in 7 series FPGAs providedifferent reference clock input options. Clock selection and availabilitydiffers slightly from 7 series GTX/GTH transceivers in that reference clockrouting is east and west bound rather than north and south bound. 只能復(fù)用鄰近的Quad的相同半部分（一個(gè)Quad分為兩半部分）（the reference clock supplied to the PLLs in a given Quad can also besourced from the adjacent Quad in the same half of the device. A Quad locatedin the top half of the device can share its two local reference clocks with theother Quad located in the top half. Similarly, a Quad located in the bottomhalf of the device can share its two reference clocks with the other Quadlocated in the bottom half.）

The GTX/GTH transceivers in 7 series FPGAs providedifferent reference clock input options. Clock selection and availability issimilar to the Virtex-6 FPGA GTX/GTH transceivers, but the reference clockselection architecture supports both the LC tank (or QPLL) and ring oscillator(or CPLL) based PLLs. 可以復(fù)用鄰近上下兩個(gè)Quad（the reference clock for a Quad (Q(n)) can also be sourced from theQuad below (Q(n–1)) via GTNORTHREFCLK or from the Quad above (Q(n+1)) viaGTSOUTHREFCLK. For devices that support stacked silicon interconnect (SSI)technology, the reference clock sharing via GTNORTHREFCLK and GTSOUTREFCLKports is limited within its own super logic region (SLR).）

The GTH transceivers in UltraScale devices providedifferent reference clock input options. Clock selection and availability issimilar to the 7 series FPGAs GTX/GTH transceivers, but the reference clockselection architecture supports two LC tanks (or QPLL) and one ring oscillator(or CPLL) based PLLs. 可以復(fù)用鄰近的上下各兩個(gè)Quad（the reference clock for a Quad (Q(n)) can also be sourced from up totwo Quads below (Q(n–1) or Q(n-2)) via GTNORTHREFCLK or from up to two Quadsabove (Q(n+1) or Q(n+2)) via GTSOUTHREFCLK.

For devices that support stacked siliconinterconnect (SSI) technology, the reference clock sharing via GTNORTHREFCLKand GTSOUTREFCLK ports is limited within its own super logic region (SLR).）

he GTY transceivers in UltraScale devices providedifferent reference clock input options. Clock selection and availability issimilar to the 7 series FPGAs GTX/GTH transceivers, but the reference clockselection architecture supports two LC tanks (or QPLL) and one ring oscillator(or CPLL) based PLLs. 可以復(fù)用鄰近的上下各兩個(gè)Quad.

對(duì)應(yīng)的時(shí)鐘源有如下區(qū)分：

① GTP對(duì)應(yīng)的Each GTPE2_COMMON in a Quad hasfour clock inputs available:

- Two local referenceclock pin pairs, GTREFCLK0 or GTREFCLK1

- Two reference clock pinpairs from the other Quad situated in the same half of the device

② 7系列的GTX/GTH對(duì)應(yīng)的Each GTX/GTH transceiver channel ina Quad has six clock inputs available:

- Two local referenceclock pin pairs, GTREFCLK0 or GTREFCLK1

- Two reference clock pinpairs from the Quads above, GTSOUTHREFCLK0 or GTSOUTHREFCLK1

- Two reference clocks pinpairs from the Quads below, GTNORTHREFCLK0 or GTNORTHREFCLK1

③ Ultra和Ultra+系列的GTx對(duì)應(yīng)的transceiver channel in a Quad hassix clock inputs available:

- Two local referenceclock pin pairs, GTREFCLK0 or GTREFCLK1

- Two reference clock pinpairs from the Quads above, GTSOUTHREFCLK0 or GTSOUTHREFCLK1

- Two reference clocks pinpairs from the Quads below, GTNORTHREFCLK0 or GTNORTHREFCLK1

④ 針對(duì)Ultra和Ultra+系列的參考時(shí)鐘源不是10個(gè)的原因詳見(jiàn)UG576和UG578。

QPLL/CPLL

QPLL的質(zhì)量比CPLL好，最好使用QPLL。

REFCLK

REFCLK的電平標(biāo)準(zhǔn)為L(zhǎng)VDS或者LVPECL，都必須有AC耦合電容，電容的作用如下：

① Blocking a DC current betweenthe oscillator and the GTY transceiver Quad dedicated clock input pins (which reduces the power consumptionof both parts as well).

② Common mode voltage independence.

③ The AC coupling capacitor formsa high-pass filterwith the on-chip termination that attenuates a wander of the reference clock.

當(dāng)輸入電平為L(zhǎng)VPECL時(shí)，需進(jìn)行直流偏置，偏置電阻的值優(yōu)先滿足晶振的要求。

當(dāng)輸入電平為L(zhǎng)VDS時(shí)，The nominal range is 250 mV–2000 mV and the nominal value is 1200mV.

When multiple clock pins are used, an external buffer can be used to drive them from the same oscillator. 當(dāng)同一個(gè)quad使用了不用的時(shí)鐘輸入引腳時(shí)，可以使用外部時(shí)鐘buffer提供外同步時(shí)鐘！！！

編輯：hfy